The present invention relates to a data processing device, an image encoding/decoding device, and a data processing system applying the same, and relates to a technique effective when applied to any of video-image reproducing and recording apparatuses such as a DVD/HDD recorder which is image compression and decompression hardware, a digital video camera, a digital camera, a mobile phone, a navigation system, and a digital television, for example.
Recently, an image encoding/decoding device has been provided with a more complicated function for supporting, for example, multi-codec processing which can support multiple kinds of image encoding/decoding algorithms such as MPEG2 and MPEG4, and has been increasing the number of registers performing initial setting, increasing a capacity of a program file, etc. In the prior art, a CPU sets each of a large number of registers within the image encoding/decoding device one by one utilizing a slave access of a bus, and therefore the initial setting operation takes a long time. Further, there arises also a problem that a data amount to be set becomes enormous and a load of the CPU increases as the number of registers increases.
Patent document 1 (Japanese Unexamined Patent Application Publication No. 2005-56033) discloses a technique to cover the setting time by providing two registers, and by using one register for current operation and the other register for setting the next operation or retaining an initial value of the register. Patent document 2 (Japanese Unexamined Patent Application Publication No. 2006-178689) discloses a technique to reduce the setting data amount and time by transferring compressed data and setting the data to the register after decompression thereof within the circuit.